1. Field of the Invention
The present invention provides a method of forming a dielectric layer on a semiconductor wafer, and more particularly, of forming a dielectric layer over a plurality of metal lines on a semiconductor wafer.
2. Description of the Prior Art
Metal lines on a semiconductor wafer are usually used for interconnecting electric devices. In order to prevent short circuiting of the metal lines, a dielectric layer of silicon oxide is usually formed to completely fill the gaps between the metal lines. The minimum line width and line space become smaller and smaller as IC technology progresses. Thus, the dielectric layer is usually formed by high-density plasma vapor deposition (HDPCVD) to ensure complete filling of the gaps. However, the surface topology of the dielectric layer formed by HDPCVD is usually quite poor as to cause the formation of voids within the subsequently deposited cap dielectric layer. These voids damage the yield rate and the reliability of IC product.
Please refer to FIG. 1, FIG. 1 is a cross sectional diagram of a semiconductor wafer with a dielectric layer formed on metal lines according to the prior art. A semiconductor wafer 10 comprises a bottom dielectric layer 12 made of silicon oxide and a plurality of metal lines 14 each having a rectangular cross section positioned on the bottom dielectric layer 12. According to the prior art, a dielectric layer 16 on the semiconductor wafer 10 is formed in a HDPCVD apparatus (not shown) with a fixed etching to deposition ratio (E/D ratio) to cover the bottom dielectric layer 12 and the metal lines 14. The E/D ratio is defined as the ratio of the etching rate to the deposition rate of the dielectric layer 16 during its formation. A large E/D ratio is used in the prior art to make sure that the dielectric layer 16 can completely fill the gaps between the metal lines. Since the etching rate depends on the ion collision angle on the surface of the semiconductor wafer, each of the portions of the dielectric layer 16 above the metal lines 16 has a triangular ridge with two slanted side-walls 17.
Please refer to FIG. 2, FIG. 2 is a cross sectional diagram of a semiconductor wafer with a cap dielectric layer formed on the dielectric layer in FIG. 1. Plasma-enhanced chemical vapor deposition (PECVD) is the method used for forming a cap dielectric layer 18 on the semiconductor wafer 10 according to prior art. A silicon oxide layer formed by PECVD with silane (SiN4) as a reactant gas is known as a PEOX layer. It is used to form the cap dielectric layer 18 and protect the electric devices and the metal lines 14.
It is a well-known fact that the PEOX layer has poor conformality and therefore voids may easily form. If the slant of the side-walls 17 is too steep, the recesses formed by the triangular ridges become deeper. Even though the PEOX layer is formed on the semiconductor wafer 10, it cannot completely fill the recesses and voids 19 are generated. Also, there is great stress between the cap dielectric layer 18 and the dielectric layer 16 because the sharper-angles of the triangular ridges is enhanced by the greater tilt angles of the slant side-walls 17. This results in a higher probability of peeling and cracking during subsequent CMP processing. Moreover, it is possible that the slurry used in the subsequent CMP process will remain in the voids 19 of the cap dielectric layer 18. The slurry residue not only reduces the yield and the reliability of the IC product, but also contaminates the whole production line in IC manufacturing.
Tetra-ethyl-ortho-silicate gas can take the place of SiH4 gas for forming a silicon oxide layer by a PECVD apparatus known as the PETEOS layer. The PETEOS layer has been proven to have better conformality leading to a lower rate of void formation inside the cap dielectric layer 18. However, the cost of forming a PETEOS layer is prohibitively high thus causing the IC product to lose its competitive edge in the marketplace. Thus, the most reasonable way for preventing the formation of voids in the cap dielectric layer 18 is to improve the topology of the dielectric layer 16, so the yield of the IC product can be increased.